As an example, a multiplex system carrying synchronous packets, each having a fixed length, is described in the copending U.S. patent application Ser. No. 540,790 filed on Oct. 11, 1983 by the Applicants and entitled "Synchronization for a digital train intended for a correct framing of received information". In that system, packets are data blocks with a fixed length of N bytes, for instance with N=16. The first byte of the packet is the header for identifying the packet being transmitted through the multiplex system. The following fifteen bytes carry the proper information. The multiplex medium is itself divided into time intervals having a fixed length which is equal to the one of a packet. A time interval may be either idle when it does contain any packet, or busy when it contains a packet. In the first case, the byte value in the time slot corresponding to the label is zero, while, for any busy time interval, it may usually be one of the remaining 255 combinations.
In PCM circuit multiplex, the time slots are implicitly identified by their positions in each multiplex frame. In a packet multiplex of the above mentioned type, each packet also occupies a constant time interval, but is also identified by an explicit address on the eight bits. A purpose of the invention is to take advantage of that analogy for providing a synchronous packet multiplex switching system.
For guidance, the TDM switches used for switching n-channel multiplex digital telephone lines are described in the technical book "La commutation electronique" (Electronic Switching) by GRINSEC, pages 247-252. In such TDM switches, the switching function makes it possible to route the contents of any time slot of any input multiplex MUXEi to any time slot of any output multiplex MUXSj. In particular, in the through-output controlled TDM switches designed to ensure a broadcasting function, the incoming time slots are stored at a well defined place in a buffer memory. A control memory, which is programmed when the communications are being established, assigns to each outgoing channel the address of the place in the buffer memory wherein the contents of the time slot will have to be transferred to the associated outgoing channel. Outgoing channels are cyclically scanned and control memory is also read cyclically.
A purpose of this invention is to provide a synchronous packet switching system, wherein the packets are considered as time intervals each with an explicit address, so that those functions may be used which exist in the through-output controlled TDM switches. Essentially, the packet switching function is given a new identification to each incoming packet which has been identified by the rank number of the incoming multiplex carrying it and its header. The new identification comprises two attributes of the same type, i.e. a new header and the rank number of the outgoing multiplex which the packet will be applied to. That is to say, the packet (e,i), e being the number of the incoming multiplex and i the header, is changed into a packet (s,j) with s being the number of the outgoing multiplex and j the new header.
In such a switching operation, the packet (e,i) must be processed before being stored in the buffer memory. Indeed, it is submitted to a "header change or header switching" which corresponds to a time slot change in a conventional TDM circuit switching. The processing is controlled by a control memory which has been programmed by the time the packet communication is established. Thus, the header i is replaced by the header j. Then, the packet (e,j) is stored at a known address in the buffer memory, depending on the write time defined by e. That address is stored in a queue associated with the outgoing multiplex s. Since the system is a through-output control system, during the outgoing multiplex scanning cycle, the queue associated with the outgoing multiplex s is scanned in order to get the address of the next packet to be carried by the outgoing multiplex s. As in TDM switches, the packet data are stored in the buffer memory.
More particularly, in the above described system, the whole packet has implicitly been submitted to a series-to-parallel conversion before being written into the buffer memory, as in TDM switches. In TDM switches, each channel is an 8-bit word. The presently available 8-bit series-to-parallel converters are fast enough to be used in those TDM switches. With respect to packet switching, each packet is obviously made of several bytes, for instance sixteen bytes as described in the above mentioned U.S. patent application. Therefore, the time required for parallel converting a whole packet is substantially longer.
Furthermore, in a packet switch, once the bytes have been parallel converted, the incoming packets carried by each multiplex are always transferred into a memory assigned to that multiplex and used as an input queue or FiFo (first in, first out) memory.
In a packet switch, the series-to-parallel converter of the sequence of parallel bytes operates at a time with a single input queue, i.e. a single input multiplex, the set of input queues having to be processed in a complete cycle, the duration of which is the series transmission duration of a packet. But FIFO memories implementing the queues are relatively slow operating components. For the series-to-parallel conversion of a packet, it is necessary to get access sixteen times to the concerned queue, which requires an excessively long time, and which limits the processing capacity of the system. It is the same at the output for the parallel-to-series conversion.
Another purpose of the invention is to overcome that slowness in order to have a packet switching matrix with a performance which is compatible with the flow rates of the videocommunication services.
According to this invention, for avoiding the mentioned waste of time, the series-to-parallel conversion of the input byte queues is replaced by excessive simultanous permutations of bytes for the set of the incoming multiplex, and for other successive simultanous permutations for the set of outgoing multiplex. Because the control logic circuitry, which comprises the control memory alone, can scan only one label per byte slot, the labels of the packets from different ingoing multiplex are chained one after the other before being processed. To this end, a time shift of one byte slot is provided in the input queues, from one queue to the following one. The series-to-parallel converter is replaced by a rotation matrix capable of performing a controllable rotation on groups of N bytes (16 bytes). The rotation order is incremented step by step, for each byte slot. At the output of the rotation matrix, data are in a "parallel-diagonal" form which will be fully explained in the following specification. The data are stored in the parallel-diagonal form in the buffer memory. The parallel-to-series converter is also made of a cyclically controlled rotation matrix which performs the reverse shifts with respect to the input rotation matrix shifts, in the reverse duration.